Wafer Foundry
Shuttle Runs (MPW - Multi Project Wafers)
System in Package (SiP), Multi-Chip Package (MCP)
Wafer FoundrySupertec offers through its ASIC/Foundry partners "mask making" and "wafer processing" as standard services, and "wafer sort", "packaging" and "LSI testing" as optional services in order to meet the needs of our diverse customer base, from wafer sort to fully packaged and tested units.
The following lineup of technologies are offers, corresponding to different types of customers' applications, 0.35um / 0.25um / 0.18um / 0.13um / 90nm CMOS and mixed-signal technologies. Copper wiring is available with 0.13um / 90nm CMOS technologies.
Our ASIC/Foundry partners offer also a broad range of resources available to SOC designers, including all back-end design services with silicon validated reference flows, a broad of IP portfolio and libraries. Further support can be offer in terms of system partition, technology, IP, and package selection trade-offs for particular application.
Combine these with our advanced process technology, extensive package and test capabilities, and the result is complete and successful one-stop shop for SOC foundry solutions.
Please contact us for more information about this service, offers processes and technologies.
Shuttle Runs (MPW - Multi Project Wafers)Supertec offers through its ASIC/Foundry partners a quick and low cost access to leading edge technologies platforms owing to Multi project wafer (MPW) program. This MPW program provides customers a pre-production service that saves costs by sharing MASK sets and wafer with other users in order to get new designs into the market quickly. It has proven cost effective for both product prototyping and IP development by allowing designers to validate the functionality and process compatibility of various IP blocks, cell libraries and I/Os, prior to design completion, especially suitable for System-on-Chip (SoC) and Analog Mix-Signal designs. This MPW program is of high quality with consistent samples as it uses the same process as that for the ASIC products.
The service includes mask making, wafer processing, and packaging with short TAT, as a standard services and it runs on a monthly basis.
Please contact us for the latest schedule and more information about this program, offers processes and technologies.
System in Package (SiP), Multi-Chip Package (MCP)“Solution that places multiple LSIs (Dies) that function as a system in the same package”
Our SiP, MCP solutions provide the most suitable products for applications requiring small size-weight, high capacity integration and high performance. These solutions bring all those factors together in one small package, by using chip stacking or side by side technology. In addition these solutions can achieve much shorter Development time than SoC. They support various applications to reduced size and cost reductions for cellular phones/portable devices and other mobile consumer electronics.(DSC, DVC etc)
Market Demands
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Higher Function |
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Higher Speed |
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Larger Scale/ Capacity |
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Miniaturization |
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Shorter Development Cycle |
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Low Cost |
Sip Advantage compared to SOC solution
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Reduced development cost |
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High yield |
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Please contact us for more information about this solution. |
