Structured ASIC

“… Performance like ASIC, Time-to-market like FPGA, with ideal Development Cost …”

Structured ASIC technology - Product Profile

Position of Structured ASIC :

 

Structured ASIC is a great solution as alternative to ASSPs, FPGA and cell-based ASICs in the mid-volume market as a results of the following: 

  • Reduces total cost (lower design services and mask cost) and Shortens Time-to market, as existent architectures shorten timing closure and solve signal integrity issues. The platforms is Pre-fabricated up to metallization and customer logic is implemented with metal mask layers, while the memory, APLLs and logic are Pre-diffused, and the IO cells are Metal programmable. Further on , all test-related
components and connections are built in so DFT is simplified.
  • Power dissipation is better than similar solutions, due to specifically developed
libraries and Clock tree architecture.
  • Similar performance to cell-based ASICs.
  • Support variety portfolio of IPs and interfaces with embedded high-speed I/O such as
SPI-4, SFI-4, SFI-5, XAUI, Fibre Channel, PCI-X, PCI-Express and Rapid I/O.
  • Variety platform of Frames for: High density, High speed integration, High speed
interfaces integration and ARM embedded.

Please contact us for more information about this products and different frame platform.

created by Bynet Software Systems