SUPERTEC

MIPI D-PHY Mixed-Signal IP

Silicon Proven

- TSMC 80GC Transmitter

- TSMC 80GC Receiver

- TSMC 130nm CIS PLLSilicon

GDS Available now

- TSMC 65LP Transmitter

- TSMC 65LP Receiver

- TSMC 65LP PLLGDS Available now

Solution – key features

- Supports MIPI®v0.9 Specifications

- 1GHz data transfer rate per lane

- HS, LP and ULPS modes supported

- Digital D-PHY integrated for interface to PPI

- LP-TX and LP-RX for bi-directional transmission in LP mode

- Dynamic impedance control for LP-TX

- HS and LP modes automatically

- Expandable to support 4 data lanes

- Built-in contention detection

- Automatic termination controls

- Integrated LDO regulators avoids external power-regulation

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Power-Regulators for SoC Integration

- Largest portfolio: more than 50 cores

- Proven silicon 130nm, 90nm, 65nm & 40nm

- 5V connect technology

- Across 8 foundries:

CHARTERED, TSMC, IBM, UMC, SILTERRA, FUJITSU, SAMSUNG, SMIC

- A complete portfolio for complete power-integration

Technology portfolio

- DC/DC Buck

- DC/DC Boost

- DC/DC Buck-Boost

- Low Drop-Out (LDO) regulators

- Ultra-low-noise linear voltage regulators

- Capacitive charge-pumps

- Li-Ion USB battery-chargers

- High-precision band-gap references

Power-ON-SoC™ portfolio

- More than 60 IP-cores across functions, process-nodes & foundries

- Spans across 130nm (30 cores), 90nm (15 cores), 65nm (19 cores) and 40nm (2 cores)

- Spans across DC/DC converters (18-cores), LDO regulators (42-cores),

Charge-pumps (6-cores) and battery chargers (3-cores)

- Silicon proven cores in 130nm, 90nm and 65nm

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ARM Microcontroller Prototyping System for Cortex-M3

Design and test your next CortexTM-M3 based platform today!

The ARM® Microcontroller Prototyping System is the latest ARM development platform and offers total flexibility to prototype your bespoke Cortex-M3 based design.
No other platform allows unrestricted access to the latest Cortex-M-class processors in FPGA. The system is delivered with a comprehensive range of tools
that allow fast and easy system design – drag and drop the supplied IP components to configure the system, or implement your own system blocks. Then
synthesise the design and update the board with a single mouse-click. The tool suite also includes system configuration utilities and a JTAG signal monitor
together with software development tools and a JTAG debug probe.

Features and benefits

- ARM Cortex-M3 processor performance @ 50MHz in FPGA

- Altera® Stratix® III FPGA for system prototyping

- CAN, FlexRay, RS232, DVI, USB, Ethernet, Audio MMC interfaces

- Example IP blocks and system configurations included

- Graphical layout and synthesis tools provided

- Comprehensive JTAG utilities for hardware monitoring and software debug

- Complete with examples and documentation

Designed in partnership by ARM and Gleichmann Research the Microcontroller Prototyping System is the most powerful and flexible platform for developing

Cortex-M-class prototypes.

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Industrial Reference Platform

Gleichmann Electronics Research is proud to announce
a new Industrial Reference Platform.

The heart of this platform is an Intel^® Atom^™ processor and an ALTERA^® ARRIA^® FPGA, connected together PCI Express to support customer specific interface and logic requirements. The system is based on the Gleichmann Hpe^® platform, an expandable base board with a range of different interfaces in a durable enclosure.

Hpe_IRP on Intel website
Hpe_IRP Intel product brief
Hpe_IRP on ALTERA website
Hpe_IRP on MSC website
Hpe_IRP on GE-Research website

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Hpe®_JTAG - Entry-level version available for less than 400 Euros

Gleichmann Electronics Research presents cost-efficient JTAG tool for easier debugging and testing of PCBs and ICs: Hagenberg (Austria) – Gleichmann Electronics Research presents its Hpe®_JTAG, a plug-and-play tool designed for the interactive debugging and testing of PCBs and ICs,

Hpe®_JTAG is delivered with an optional USB-JTAG cable. It supports all obligatory JTAG instructions (SAMPLE, EXTEST, BYPASS) as well as INTEST. Additionally, arbitrary user register accesses can be defined.

To make it easier for users to locate relevant signals, signal names can be imported from BSDL or pin files, which were generated during the FPGA synthesis. As a result, it can be checked at a glance whether, for example, reset and enable signals are set correctly, clock inputs are toggling or data and address buses are stuck at a certain value. As opposed to measurements with an oscilloscope or logic analyzer this observation is absolutely non-intrusive.

A python scripting interface allows users to add functionality to the tool or to automate repetitive tasks. Any user defined JTAG access is allowed - users are only limited by their imagination.

A free demo version of Hpe®_JTAG is available now and can be downloaded from:
http://www.ge-research.com/hpe_jtag.html.

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Please contact us for further information about this device